1. Field of the Invention
The present invention relates to a semiconductor memory device for a data processing system. A semiconductor memory device according to the present invention is applied to, for example, a computer incorporating a cache memory,
2. Description of the Related Art
Since a main memory of a computer is generally connected to a processor through a bus and is given a large capacity by using a dynamic random access memory (DRAM), a long access time is required. In order to reduce the access time, a cache memory constituted by a high-speed static random access memory (SRAM) is used. Data read from the main memory is temporarily stored in the cache memory and the supply of the same data is carried out from this cache memory, thereby reducing the total memory access time.
It is, however, difficult to produce a large-capacity cache memory since it is constituted by an SRAM. In general, the capacity of the cache memory corresponds to a part of the main memory. The main memory is divided into a plurality of sets, and a cache memory is constituted by one, two or four of such sets. For example, one block is constituted by 16 bytes; one set is constituted by 512 blocks; and a main memory is constituted by 524,288 sets. The address portion A0 to A3 allows a selection of one of the 16 bytes of one block; the address portion A4 to A12 allows a selection of one of the 512 blocks of one set; and the address portion A13 to A31 allows a selection of one of the 524,288 sets of the main memory.
Data is stored in the cache memory in units of 16 bytes, as one block of the main memory. The address portion required for storing data in the cache memory is the same lower address portion A4 to A12 of the main memory. In this case, one of the 524,288 sets of the main memory to which the selected block belongs cannot be specified. To prevent inconvenience, the upper address portion A13 to A31 is stored in another memory as a tag memory. The tag memory is accessed by the lower address portion to read the corresponding upper address portion. The upper address portion for accessing the main memory is compared by a comparator with the upper address portion read from the tag memory. If a coincidence between these address portions is established, storage of the desired data in the cache memory has been detected. The cache data memory is then accessed by the lower address portion and the corresponding data is output.
Assume that the main memory data is stored at the same upper address portion of the data memory as the lower address portion A4 to A12 of a given block of the main memory, in units of 16 bytes as one block, and that at the same time, the upper address portion A13 to A31 of the given one block is written in the tag memory. Under these assumptions, the data memory has a capacity corresponding to four sets of the main memory. Therefore, the cache memory can store a maximum of four blocks having the same lower address portion A4 to A12.
The cache memory thus has a capacity of a plurality of sets. However, if all data having the address portion A4 to A12 has already been stored in the cache memory and one block having the address portion A4 to A12 is to be read from a given set of the main memory, the content of the cache memory must be purged. For this purpose, an LRU (Least Recently Used) is often used as a replacement algorithm.
The upper address portion is stored in the tag memory. When the upper address portion of the address data for accessing the main memory coincides with the upper address portion read from the tag memory, storage of the corresponding data is detected. However, when the power source is switched on, the memory data is in a random state. In this state, the upper address portion for accessing the main memory may accidentally coincide with the data read from the tag memory, and storage of the corresponding data in the cache memory is erroneously detected As a result, the random data is undesirably read from the data memory.